CONCEPT FOR HERMETIC, LOW HEAT, MINIMUM INDUCTION PACKAGING
Thermal management, thermo-mechanical design and low cost manufacturing are the key factors for power electronic applications addressing a mass market like electro mobility. With the introduction of the new semiconductor materials GaN and SiC the reduction of parasitic inductances due to short switching times gets also more important. 3D power modules have many advantages, but the manufacturing process is complex. Furthermore, humidity and corrosive atmosphere both cause degradation and failures of the semiconductor elements.
Here we present a 3D buildup concept for hermetic packaging with optimized thermal cou- pling and minimized induction for power modules. The switches (MOSFETs or IGBTs) and the free wheeling diodes are soldered or sintered between at least two DBC (direct bonded copper) substrates. This allows a dissipation of the heat in two directions, which reduces the thermal resistance by a factor of up to two. Additional no wire bonds are needed. They are responsible for the main part of the parasitic inductance and represent a huge failure risk for planar power modules.
- Power Electronics
Figure: Example hermetically encapsulated sandwich module according to invention with optimized materials, geometries in respect to minimization of parasitic induction and optimized thermomanagement.
(1) M. SCHMIDT ET. AL. „POWER ELECTRONIC PACKAGE FOR DOUBLE SIDED COOLING UTILIZING TILE-LEVEL ASSEMBLY“, PCIM 2017